A High-Speed Time-Interleaved SAR ADC
Date Issued
2016
Date
2016
Author(s)
Huang, Wei-Chia
Abstract
Analog-to-digital converter (ADC) has to operate at ultra-high speed with low to medium resolution in the next-generation wireless communication systems. A 6-bit 4.5 GS/s time-interleaved SAR ADC in 40 nm CMOS general–process (GP) technology is proposed. By combining the front-end input buffers and the grouping technique into the time-interleaved architecture, the input capacitance effectively decreases and the available settling of input buffers increases. The proposed 16-channel time-interleaved SAR ADC achieves the performance of high-speed sampling rate and high input bandwidth. A zero-crossing detection technique is employed to correct timing skew among sub-ADCs. Gain and offset mismatches between sub-ADCs are calibrated in the digital domain. Asynchronous processing and monotonic capacitor switching technique used in the single-channel SAR ADC make the sub-ADC high speed and power-efficiency. Furthermore, AWCA technique solves the dynamic offset problem of the comparator in the sub-ADC. The measurement results show that ADC exhibits DNL of +0.17/-0.29 LSB and INL of +0.20/-0.18 LSB at 4 GS/s with Fin of 50 MHz. SNDR and SFDR are 32.15 dB and 41.04 dB at 4.5 GS/s with Fin of 1 GHz. The power consumption is 24.9 mW at 1.2 V supply voltage. As a result, the FoM (Power/2ENOB/FS) is 159 fJ/conversion-step. The whole chip including pads occupies 1.275 mm2 while area of core circuit is 0.195 mm2.
Subjects
analog to digital converter
time-interleaved
SAR
grouping technique
high input bandwidth
Type
thesis
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ntu-105-R02943026-1.pdf
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