System-level Power Estimation for Digital Signal Processor
Date Issued
2009
Date
2009
Author(s)
Wu, Xin-Chuan
Abstract
In this thesis, we present an improved instruction-level power estimation tool to evaluate the power consumption associated with a software code for an embedded VLIW digital signal processor (DSP). Instruction-level power estimation is widely used in software optimizations, of which the speed is order of magnitude faster than circuit- and gate-level simulations and the estimation error is within 10-20%. This work presents its application on an embedded VLIW DSP. The simulation time is reduced from tens of minutes for a kernel-level task to only few seconds and the estimation error is about 4-14%. To estimate the power consumption of target DSP running a program, we partition a target DSP into three major parts, DSP core, data memory and other components that have fixed power consumption. For DSP core, based on the usage of the hardware resources, it can be separated into shared hardware resources and isolated hardware resources, and we model the power consumption respectively. For data memory, we observe two major factors to affect the power consumption of data memory: (1) the number of read/write operation. (2) the power consumption of each read/write operation. We propose an improved power model for instruction-level power estimation of VLIW DSP, which takes into account the memory accesses and the variable-length instructions that are common in such architectures. In our experiments, the proposed approach reduces the maximum estimation error to only 4% and the simulation overheads are neglectable.
Subjects
Instruction-level power estimation
VLIW
digital signal processor
Type
thesis
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