Hybrid Functional Verification Methodology for Alpha Processor Using RTL Symbolic Simulation
Date Issued
2008
Date
2008
Author(s)
Chen, Huan-Wen
Abstract
Verification is an important part of the modern IC design, especially functional verification, which is responsible for 40% of the failure. There are two major verification methods that are being commonly used, simulation-based and formal approach. As the increasing complexity of modern design, the goal of proving functional correct is becoming more and more difficult to obtain. As the result, we introduce a scalable hybrid verification methodology to leverage the advantages of both simulation and formal approaches. The primary advantage of our method is that it can be implemented easily. We use a hybrid logic/symbolic simulator called Insight to transform the circuit into a SAT problem under restricted condition. And then, use an SAT solver to verify if it is satisfiable to prove its functional correct.
Subjects
Alpha
microprocessor
formal
simulation-based
verification
hybrid methodology
functional verification
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
index.html
Size
23.27 KB
Format
HTML
Checksum
(MD5):aa508f9cebee73fa2ad07ffefab9f02e