Multi-Mode Viterbi Decoder VLSI Design for Wireless Communication Systems
Date Issued
2007
Date
2007
Author(s)
Huang, Yu-Chuan
DOI
zh-TW
Abstract
The mobile handheld devices have been widely used as the application of the wireless communication systems. The requirement of the data throughput and the effective range of the handheld devices have been increased at the same time. It makes the needs of the long-range communication systems, such as IEEE 802.16 (WiMAX), 802.16e (mobile WiMAX), 3GPP of the mobile communication system, and the HSDPA (high speed downlink packet access), increase rapidly. In order to access different communication systems, the mobile communication devices suitable for multiple standards will be an important trend in the coming future.
In the standards mentioned above, Viterbi decoder is one of the essential modules of the channel CODEC. Though the error correcting performance of the Viterbi decoder may not better than the Turbo or LDPC decoders, Viterbi decoders are still widely adopted in the modern communication systems due to its lower power consumption and lower hardware requirements. As the reasons mentioned above, we propose several techniques for improving the Viterbi decoder and a structure suitable for a multi-mode Viterbi decoder design.
In this thesis, we were devoted to two fields. First, we propose two techniques of modifying the structure of the survivor memory units (SMU), which can reduce the power consumption and the decoding latency. Second, we propose a Viterbi decoder structure for fulfilling the specification of the WiMAX, 3GPP, and HSDPA at the same time. We use the 0.13 technology of the cell-based design flow to implement our proposed Viterbi decoder chip.
Subjects
維特比
解碼器
無線通訊
Viterbi
WiMAX
3GPP
HSDPA
SMU
Type
thesis
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