A 10-bit 300-Msample/s Pipelined Analog-to-Digital Converter with Open-loop Residue Amplification an Digital Background Calibration
Date Issued
2005
Date
2005
Author(s)
Wang, Wei-Der
DOI
en-US
Abstract
By aggressive device scaling in modern integrated circuit technology, the computing ability of digital circuits increases significantly. But the low power supply and relative high threshold voltage of transistors exhibit design difficulties for analog circuit. Analog-to-digital converters provide the link between the analog and digital world. Due to their frequent use of analog and mixed analog-digital operations, A/D converters often appear as the bottleneck in data processing applications, limiting the overall speed or precision.
In this thesis, we describe the design and simulation of a 10-bit 300-MSample/s pipelined ADC with open-loop residue amplification and digital self-calibration. First, a traditional sample-and-hold circuit is in front of the ADC. For digital calibration algorithm, 1-bit random number is added to 4-bit flash ADC stage and over-range stage. We employ open-loop amplifiers in two residue amplification stages to save power and area. Using a constant- biasing technique, the open-loop amplifier is process-and-temperature insensitive. The gain error and nonlinearity of open-loop amplifiers are removed by digital calibration algorithm.
Subjects
類比數位轉換器
analog
digital
converter
Type
thesis