Development of Module Library for Communication/Signal Processing System Chips
Date Issued
2000-07-31
Date
2000-07-31
Author(s)
DOI
892215E002029
Abstract
The main objective of the project is
to developing a parametric module
design framework that is suitable for
designing the baseband signal
processing/datapath units. The
framework is composed of C++
hardware related data classes, parametric
module libraries and the cell libraries. In
this framework, designers specify the
system parameters and use the module
generators to generate the C++ function
simulating code and gate-level Verilog
code used for physical design. The
design flow achieves high-level
abstraction and high reusability, short
design time, and less prone to human
errors. In the first year we focused on the
design and verification of the cell
libraries using TSMC 0.6/0.35mm
technologies. Moreover, we proposed a
C++ parametric module class, and use
the class to design several simple
modules. In the second year we try to
design more modules, provide module
with a variety of architectures, refine the
hardware data classes to increase the
efficiency of function simulation, and
slightly modify the design framework.
On the other hand, we integrate the
module libraries into conventional
C/C++ window-based programming
environments to provide a friendly user
interface and better class encapsulation.
Subjects
module library
cell library
parametric module
Publisher
臺北市：國立臺灣大學電機工程學系暨研究所
Type
report
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