IEEE 1500 Compatible Test Wrapper Design and Validation for At-Speed Delay Testing

In this thesis, two delay fault test methods are proposed,G1P2 and G2P2. G1P2 is a delay fault test method which may save test area and test time. G2P2 is a precise At-Speed delay fault test method. Our delay fault test methods would need some test points. A test point selection method is presented.An automatic testbench generator for testing a SoC(System on Chip) with IEEE 1500 wrapped cores is implemented. The generated testbench is flexible for testing the SoC in either single stuck-at fault model or delay fault model test applications. A CTL generator for generating SoC test patterns is also implemented.