Designs of signal-ground bump-patterns for minimizing the simultaneous switching noise in a ball grid array
Journal
IEEE 17th Topical Meeting on Electrical Performance of Electronic Packaging
Pages
15-18
Date Issued
2008-10
Author(s)
Abstract
This paper proposes a design methodology to achieve the signal-ground bump-patterns with the minimized simultaneous switching noise (SSN) in a ball grid array (BGA) through the bump assignment optimization. By a simplified scheme for the equivalent model, the full-transistor circuits along with the transmission lines through the chip-packaging interconnect are constructed and validated. With the Genetic Algorithm, the optimization of bump patterns can be thus determined to achieve the minimal inductive effects in the improved suppression of SSN for a large-scale BGA demonstration.
SDGs
Type
conference paper