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College of Electrical Engineering and Computer Science / 電機資訊學院
Electronics Engineering / 電子工程學研究所
Pulsed-latch aware placement for timing-integrity optimization
Details
Pulsed-latch aware placement for timing-integrity optimization
Journal
Design Automation Conference
Pages
280-285
Date Issued
2010
Author(s)
Chuang, Y.-L.
Kim, S.
Shin, Y.
YAO-WEN CHANG
DOI
10.1145/1837274.1837346
URI
http://www.scopus.com/inward/record.url?eid=2-s2.0-77956219273&partnerID=MN8TOARS
http://scholars.lib.ntu.edu.tw/handle/123456789/358159
Type
conference paper