Design of DMT Baseband Processing Architecture for High-Speed DSL
Date Issued
2002-07-31
Date
2002-07-31
Author(s)
DOI
902218E002039
Abstract
This project presents the architecture
design, IC design and implementation of a
VDSL transceiver for DMT-based VDSL
systems. We propose an transceiver
architecture for ETSI VDSL standard using
discrete multi-tone modulation (DMT).
According to Channel model and
impairments defined in the standard, such as
additive white Gaussian noise (AWGN), near
end crosstalk (NEXT), far end crosstalk
(FEXT), radio frequency interference (RFI)
and impulse noise, algorithms for symbol
boundary estimation, sampling clock offset
estimation and compensation, fast Fourier
transform(FFT), channel estimation and
equalization, and forward error correcting
code (FEC) decoder are designed and
integrated into receiver architecture. Fixed
point system simulation results show that the
proposed receiver architecture is capable of
very high-rate transmission in digital
subscriber loop channels.
Subjects
Transceivers
Wideband data
communication
communication
OFDM, Digital
Subscriber Loop
Subscriber Loop
DMT
Publisher
臺北市：國立臺灣大學電機工程學系暨研究所
Type
report
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