IEEE 802.11a 無線區域網路CMOS 5.25GHz發射機前端之設計與實作
The Design and Implementation of the front-end of a CMOS 5.25GHz transmitter
Date Issued
2005
Date
2005
Author(s)
Chen, Chang-Hung
DOI
en-US
Abstract
The CMOS RF transmitter was implemented to meet the requirement of IEEE 802.11a Wireless LAN Systems are presented in this thesis. The circuit design in this thesis is divided into two main parts including mixer and power amplifier, and that all implemented with the process of TSMC 0.18um 1P6M CMOS to show the higher performance in deep sub-micro process and overcome the difficulties we met.
The first main part is on the design of up conversion mixer. We based on the Gilbert Cell structure and used base-band input signal of fully differential quarter to direct up conversion. Since this architecture modulates signal without an IF section circuit, the low frequency (Base-band) signal is direct up conversion to high frequency (RF). So this architecture can omit the design of IF circuit. Even though, since the frequency of transmitter is close to local oscillator, The leakage problem and injection pulling phenomenon becomes the drawbacks of this architecture that we must solve and overcome. Compared with the conventional architectures of mixer, we presented the circuit technique of current reuse, combined with Gilbert cell and architecture of differential balance. After all, this improved mixer has better performance in conversion power gain, noise figure, isolation and linearity for applied in IEEE 802.11a WLAN standard.
The second main part is on the design of power amplifier. We adopt the two stage cascade with capacitance compensation schemes to improve the power gain and linearity of CMOS power amplifier for WLAN applications of IEEE 802.11a. The output power in this circuit design is over 20dBm(100mW) and fabricated in a standard 0.18um single-poly-six-metal (1P6M) RF CMOS process of TSMC. Compared with the conventional CMOS PAs used the thick oxide devices, The improved circuit can have the higher performance since the minimum channel length of thick oxide devices is 0.35um. But there are two main issues in the design of power amplifier in submicron CMOS process, namely, oxide breakdown and hot carrier effect. On the other hand, are reliability and lifetime issues of the circuit products. So, in this thesis, the self-biased technique is presented that relaxes the restriction due to hot carrier degradation in power amplifier and alleviates the need to used thick-oxide transistors that have poor RF performance compared with the standard transistors available in the same process.
Since the linearity requirement of the modulation signal in OFDM and 64-QAM for IEEE 802.11a is higher than the others, adopt the NMOS diode linearizer to improve the linearity in this design. Compared with the other linaer technique, for example, PMOS linearizer. There is no DC current consume in the improved method, and save much chip area compared with the conventional method of inductor biased. In addition, included the parallel inductor compensation technique to absorb the parasitical capacitance effect, makes the power amplifier have the higher performance in power gain.
Our laboratory centred on the research of front-end circuit design. For the concept of SOC, we adopt the process of CMOS that can integrate with digital circuit. In the future, this transmitter will can complete in a signal chip of 802.11a transceiver with receiver and frequency synthesizer.
Subjects
直接升頻轉換
平行電感補償技術
電流回收
功率放大器
混波器
自我偏壓技術
IEEE 802.11a
NMOS二極體線性器
NMOS diode linearizer
self-biased technique
current-reuse
parallel inductor compensation technique
Power amplifier
Mixer
Direct-up Conversion
Type
thesis
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