A Low Power Test Pattern Generation Methodology for Scan Testing
Date Issued
2007
Date
2007
Author(s)
Hu, Kai-Shun
DOI
en-US
Abstract
Average and peak power management has become a serious challenge for scan-based testing. This thesis proposes a test pattern generation methodology that reduces the power dissipation during the shift and capture cycles of conventional scan testing. The proposed methodology utilizes a power-constrained ATPG engine and a dynamic compaction scheme to generate partially specified low power patterns. Then, X-filling together with test pattern ordering is employed to enhance the achievable power reduction. Besides, a mechanism of integration with commercial ATPG is proposed which iteratively replaces the high power consumption patterns with low power ones. Furthermore, the proposed low power test pattern generation methodology can be extent to various fault models, different test application scheme, and different test application conditions. The proposed technique is validated using ISCAS89 benchmark circuits.
Subjects
掃描鏈
功率
自動測試圖樣產生
scan chain
low power
ATPG
Type
thesis
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