System Level Assertion-Based Verification Environment for PCI/PCI-X and PCI-Express
Date Issued
2004
Date
2004
Author(s)
Yu, Chien-Chih
DOI
en-US
Abstract
Circuit design becomes more and more complicated in the system on chip (SoC) due to increasing capacity of integrating gates into one chip. Verification takes a major part of non-recurrent engineering (NRE) cost of entire design flow. Basically there are two major problems exist in current verification procedure. Traditional register transfer level (RTL) verification method could take about 60% work of design cycle. Another issue is how to integrate each component into a single environment and co-verify all devices simultaneously.
This thesis describes a new verification environment with assertion-based technique and with firmware layer to provide a system level verification. Cores of this verification tool are bus functional models, bus protocol monitor, firmware layer software, and a set of assertion checkers called TestWizard. We developed a platform to verify the behavior of PCI and PCI-Express devices that can test all behaviors efficiently. A set of performance evaluation tools are be developed at the same time. By applying these performances tools, the verification environment helps designers not only to verify the correctness of circuit function, but can help hardware designer to evaluate the performance in a user-defined condition.
From experimental results, the functional coverage for processing all compliance test scenarios in this verification environment is very high and firmware layer model work very well. The results also light the possibility of checking cross-protocol transaction. This verification system is proved to be effective and efficient in the real world.
Subjects
驗證
PCI-Express
PCI
verification
Type
thesis
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