Dual-block-pipelined VLSI architecture of entropy coding for H.264/AVC baseline profile
Journal
2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, VLSI-TSA-DAT
Journal Volume
2005
Pages
271-274
Date Issued
2005
Author(s)
Abstract
Direct VLSI implementation of context-based adaptive variable length coding (CAVLC) for residues, as a modification from conventional run-length coding, will lead to low throughput and utilization. In this paper, an efficient CAVLC design is proposed. The main concept is the two-stage block pipelining scheme for parallel processing of two 4/spl times/4-blocks. When one block is processed by the scanning engine to collect the required symbols, its previous block is handled by the coding engine to translate symbols into bitstream. The dual-block-pipelined architecture doubles the throughput and utilization of CAVLC at high bitrates. Moreover, a zero skipping technique is adopted to reduce up to 90% of cycles at low bitrates. Last but not least, exponential-Golomb coding for other general symbols and bitstream encapsulation for network abstraction layer are integrated with CAVLC engine as a complete entropy coder for H.264/AVC baseline profile. Simulation results show that our design is capable of real-time processing for 1920 /spl times/ 1088 30fps videos with 23.6K logic gates at 100MHz.
SDGs
Type
conference paper