Yield Analysis of Lumped-Element Matching Networks and A Q-Band CMOS Balanced Amplifier Design
Date Issued
2006
Date
2006
Author(s)
Lee, Yi-Lin
DOI
en-US
Abstract
Yield is an essential consideration while volume production and the improvement of fabrication yield means that the production cost can be reduced. For radio frequency (RF) circuits, matching network is the key of circuit performance, and it has been proved that the matching network has strong relationship with yield [8]. However, only selecting matching topology cannot guarantee a high-yield design.
The first part of this thesis is focused on the yield analysis of two-element-lossless- lumped matching networks. We use the Monte Carlo method to plot the yield distributions in Smith chart for each matching topology. These provide the circuit designer a guideline to select matching network. Moreover, we propose a method to estimate yield from the calculation of matching path length in Smith chart. By this approach, the designer can choose the matching points with yield consideration at the initial design stage.
The second part is a Q-band balanced amplifier design with the standard bulk 90-nm CMOS process. Balanced amplifier has excellent input and output return losses, and it is a good structure from the perspective of yield. The measured results show this balanced amplifier has a very broadband gain response and good return losses at Q-band. A single-ended amplifier is fabricated as well for verification, and it shows a very flat and broadband gain response with reasonable output power. With the thin-film microstrip technique, both amplifiers have very compact sizes. To our best knowledge, this is the first balanced amplifier employing the standard bulk CMOS technology. Our work shows that the standard bulk CMOS process is another candidate for MMW bands front-end component design.
Subjects
集總元件匹配
良率
金氧半互補式電晶體
平衡式放大器
Lumped-Element Matching Networks
Yield
CMOS
Balanced Amplifier
Type
thesis
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