Polarity change of threshold voltage shifts for n-channel polycrystalline silicon thin-film transistors stressed by negative gate bias
Journal
ECS Transactions
Journal Volume
16
Journal Issue
10
Pages
163-167
Date Issued
2008
Author(s)
Huang, C.-F.
Yang, Y.-J.
Peng, C.-Y.
Sun, H.-C.
Liu, C.W.
Hsu, Y.-C.
Shih, C.-C.
Chen, J.-S.
Abstract
The negative bias instability on p-channel and n-channel polycrystalline silicon thin-film transistor is investigated. Negative threshold voltage shift is observed in p-channel TFTs and is attributed to the positively charged donor type interface traps. On the other hand, polarity change of threshold voltage shift is observed in n-channel TFTs, suggesting two competing mechanisms. Negatively charged acceptor type interface traps are the dominant factor for the positive threshold voltage shift. As the gate stress voltage increases, accumulated holes are trapped in the insulator via Fowler-Nordheim tunneling and are responsible for the negative threshold voltage shift. The stress-induced hump effect is attributed to higher electric filed at the edge transistors as compared to channel transistor along the channel width direction.
SDGs
Type
conference paper