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A 1.2V High-Speed Single-Channel Pipelined A/D Converter
Date Issued
2010
Date
2010
Author(s)
Cheng, Wei-Chih
Abstract
The pipelined ADCs with the digital calibrations have been researched in recently years. In this thesis, a gain-error self-calibration technique is presented to allow low-gain operation amplifiers (opamps) to use in high-precision pipelined ADCs. The proposed technique reduces gain error by using a calibration capacitor array. It adjusts the feedback factor; therefore, the closed-loop gain is calibrated. In the circuit design, 39.1dB open-loop gain opamps can be used for a 10-bit pipelined ADC. Only 192 clock cycles are required for the proposed foreground self-calibration technique.
According to the measurement results, the prototype ADC exhibits a DNL of +0.77/-0.55LSB and an INL of +1.45/-1.03LSB at the sampling rate of 40MS/s. With 20MHz input frequency, the SNDR and SFDR achieve 54.97dB and 63.96dB at 80MS/s. The SNDR and SFDR are 53.43dB and 61.8dB at 320MS/s with 40MHz input. The power consumption is 47.2mW at 1.2V supply. The active area is 0.21mm2 and whole chip with pads occupies 0.93mm2.
According to the measurement results, the prototype ADC exhibits a DNL of +0.77/-0.55LSB and an INL of +1.45/-1.03LSB at the sampling rate of 40MS/s. With 20MHz input frequency, the SNDR and SFDR achieve 54.97dB and 63.96dB at 80MS/s. The SNDR and SFDR are 53.43dB and 61.8dB at 320MS/s with 40MHz input. The power consumption is 47.2mW at 1.2V supply. The active area is 0.21mm2 and whole chip with pads occupies 0.93mm2.
Subjects
Pipelined analog-to-digital converter (ADC)
gain-error
low-gain opamp
self-calibration.
Type
thesis
File(s)
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Name
ntu-99-R96943142-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):ddefb1aacdf14a7e35284cff895247e9