Efficient systolic architectures for 1-D and 2-D DLMS adaptive digital filters
Resource
Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on
Journal
Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on
Pages
-
Date Issued
2000-12
Date
2000-12
Author(s)
Van, Lan-Da
Feng, Wu-Shiung
DOI
N/A
Abstract
In this paper, we propose two efficient systolic architectures for 1-D and 2-D Delay Least-Mean-Square (DLMS) adaptive digital filters. Using our developed architectures, higher convergence rate and Signal-to-Noise Ratio (SNR) than those of the conventional DLMS structure can be obtained without sacrificing the properties of the systolic architecture. Furthermore, the adaptive digital filters operate at the highest throughout due to the new tree-systolic processing element. Besides, based on our proposed optimized rule, one can easily design Nth tap and window size N/spl times/N systolic adaptive digital filters with the compromise of minimum delay and high regularity under the constraint of the maximum number of tap-connections of the feedback signal.
Type
journal article
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