Parallel implementation of convolution encoder for software defined radio on DSP architecture
Journal
2009 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2009
Pages
180-186
Date Issued
2009
Author(s)
Abstract
The question of how to efficiently implement bit-oriented operations such as convolutional encoding in a word-based processor platform is investigated. Our approach is to treat each word as a vector of individual bits. By reformulating a bit-oriented algorithm in vectorized format, it is shown in this work that significant speed-up of execution of such an algorithm can be achieved. Toward this goal, an efficient code generation design methodology is proposed to leverage the effort of common sub-expression elimination (CSE). The task of efficient vector-oriented code generation then becomes a pattern matching problem. The vectorization approach is demonstrated by the convolutional encoding portion of the IEEE 802.11a (WiFi) standard, implemented in C language on a Sandbridge Technologies copy Inc. SB3010 baseband processor evaluation board, and more than 90% instruction cycle reduction is observed.
Type
conference paper