Jitter-Improved Techniques for PLLs in Nano Scale CMOS Process
Date Issued
2011
Date
2011
Author(s)
Hung, Chao-Ching
Abstract
The continuous scaling of CMOS technology has opened the opportunity to integrate high-speed circuits operating at tens of gigahertz together with the large digital portion of modern communication systems. However, the order of the leakage current increases dramatically, which causes additional jitters in phase-locked loop. In addition, the digitalized phase-locked loop can reduce the design time from one process to another, have more tolerances to the noise, provide a variety of calibrations in digital way. Therefore, it is worth to investigate how to design an all-digital phase-locked loop in RF systems.
First of all, a leakage calibration for phase-locked loops is presented. By using the proposed circuit and design methodology, the jitter due to the leakage current and chip area are both reduced. Fabricated in a 65nm CMOS process, the IC prototype achieves a RMS jitter of 3.1ps comparing with unlocked state initially. It consumes 10 mW from a 1.2 V supply and occupies an area of only 0.14 mm2. Next, an optimal methodology is proposed to achieve smaller chip area, less power consumption due to leakage current, and less noise coupling from power supply. Fabricated in a 65nm CMOS process, the IC prototype achieves a RMS jitter of 5.13ps comparing with unlocked state initially. It consumes 3.6 mW from a 1.2 V supply and occupies an area of only 0.065 mm2.
As everyone knows, fractional-N frequency synthesizers are the key circuits to provide the clocks in RF systems. Finer frequency hopping is achieved by using the delta sigma modulation. However, the quantization noise of the delta sigma modulator and the nonlinearity of the phase frequency detector and charge pump make the phase noise of the frequency synthesizer more worse. In order to solve these two problems, an idea of noise filtering is proposed to reduce these two impacts. Fabricated in 90nm digital CMOS technology, the overall frequency synthesizer consumes 30mW from a 1V supply. The integrated phase noise is improved from 2.045。 to 1.343。.
Finally, a 40GHz all digital phase-locked loop is proposed. In order to reduce the jitter, a novel varactor topology is proposed. Therefore, finer frequency resolution of digital controlled oscillator is achieved. To authors’ knowledge, the operation frequency of this work is the highest in the world. In addition, the known drawback of the bang-bang phase detector is longer lock time. In order to reduce the lock time substantially, a modified bang-bang operation is proposed. Fabricated in 90nm CMOS technology, the all digital phase locked loop consumes 46mW from a 1.2V supply. The chip area is 0.3 mm2. The lock time is 15us. The RMS jitter is 300.87fs.
Subjects
jitter-improved techniques
PLL
nano scale CMOS process
Type
thesis
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