MARS-Multiprocessor architecture reconciling symbolic with numerical processing-a CPU ensemble with zero-delay branch/jump
Resource
VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
Journal
VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
Pages
-
Date Issued
1989-05
Date
1989-05
Author(s)
DOI
N/A
Abstract
The design of CPU (central processing unit) chips for the MARS project is described. They are the IFU (instruction fetch unit), IPU (integer processing unit), and LPU (list processing unit). The IFU is devised to interleave instruction fetch and execution, and thus to achieve coordinated execution among datapath chips. The IPU is the main computing engine for integer operations and operand address calculation. By using dual-instruction buffers, a reserved phase for branch/jump target fetch, and instruction decode peeping, the architecture can support almost-zero-delay branching and super-zero-delay jump. The LPU handles a Lisp runtime environment, dynamic type checking, and fast list access. In this architecture, the critical path of complex register file access and ALU operation is distributed over the LPU and IPU, and list tracing can be executed quickly by the nondelayed car or cdr instructions.
SDGs
Other Subjects
Integrated Circuits, VLSI--Design; CPU Chips; Microarchitecture; Multiprocessor Architecture; Numerical Processing; Symbolic Processing; Computer Systems, Digital
Type
conference paper
File(s)![Thumbnail Image]()
Loading...
Name
00068647.pdf
Size
488.22 KB
Format
Adobe PDF
Checksum
(MD5):4bf14212b2632a948b6d961d4a4b1791