An 80-GHz Phase-Locked Loop for MillimeterWave Application in 40-nm CMOS
Part Of
APCCAS and PrimeAsia 2024 - 2024 IEEE 20th Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, Proceeding
Start Page
293
End Page
296
ISBN
979-835037877-1
Date Issued
2024-11-07
Author(s)
DOI
10.1109/APCCAS62602.2024.10808473
Abstract
An 80-GHz charge-pump phase-locked loop (CP-PLL) for millimeter-wave applications is presented in this paper. To support high-frequency operation, the feedback division chain is composed of two stages of divide-by-2 injection-locked frequency dividers (ILFD), which provide a wide locking range without adding system complexity, followed by a current-mode-logic divider (CMLD), true-single-phase-clock (TSPC) divider and static CMOS dividers. The VCO adopts a class-D current-source-free structure for low-noise consideration. Fabricated in a 40-nm CMOS technology, the implemented CP-PLL operates at 76.7 GHz-83 GHz; the locking range is 7.9%. It consumes 38.3 mW from a 0.9-V supply voltage, and the output power is -2.5 dBm. The phase noise at 1-MHz and 10-MHz offset frequencies are - 8 2dBc/Hz and -107.2 dBc/Hz, respectively. The circuit achieves a reference spur of -51 dBc. With an integrated jitter of 355 fs, and the FoM-jitter is -233.2. The CP-PLL core area occupies 0.33 mm2
Event(s)
20th IEEE Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, APCCAS and PrimeAsia 2024
SDGs
Publisher
IEEE
Type
conference paper