The Analysis of Through Silicon Via (TSV) in 3D IC and Application on Power Integrity Design
Date Issued
2011
Date
2011
Author(s)
Tang, Shao-You
Abstract
With the fast development of the integrated circuit, the techniques for packaging high-density chips in advanced high-speed system have hit the wall recently. Therefore, how to keep conforming to the Moore’s Law in 2D packaging is becoming more and more critical, and that’s why the technique involving 3D technology emerges. Among all of the possible solutions for 3D IC, through silicon via (TSV) is the most promising one in the future because it can effectively solve the issues like long interconnection path, high power consumption, and high I/O pin density. It is the basic electrical properties and application of TSV that constitute this thesis.
The most significant feature of TSV is the layer of dielectric surrounding the inner conductor of TSV. This dielectric layer can be characterized with the capacitance of coaxial transmission lines, which has considerable impacts like the low-loss behavior at low frequencies, slow-wave mode, characteristic impedance, and the electric field distribution. In addition to the fundamental characteristics of TSV, the equivalent circuit model of a system containing multiple TSVs will also be investigated.
In printed circuit boards (PCB), the electromagnetic bandgap (EBG) structure has been proved to be an effective solution of suppressing the simultaneous switching noise (SSN). Besides the application to PCB, EBG structure can also be implemented inside the power/ground grid within chips to isolate noise. The innovative concepts of designing the EBG structure in chips will be presented in this thesis.
Subjects
3D IC
Through Silicon Via
TSV
Power Integrity
Type
thesis
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