Pulsed-latch aware placement for timing-integrity optimization

Journal

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Journal Volume

30

Journal Issue

12

Pages

1856-1869

Date Issued

2011

Author(s)

Chuang, Y.-L.

Kim, S.

Shin, Y.

DOI

10.1109/TCAD.2011.2165717

URI

http://www.scopus.com/inward/record.url?eid=2-s2.0-82155192308&partnerID=MN8TOARS

http://scholars.lib.ntu.edu.tw/handle/123456789/365148

Type

journal article