A programmable VLSI architecture for 2-D discrete wavelet transform
Resource
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Journal
The IEEE International Symposium on Circuits and Systems, ISCAS 2000 Geneva.
Pages
-
Date Issued
2000-05
Date
2000-05
Author(s)
DOI
N/A
Abstract
Many VLSI architectures for computing the discrete wavelet transform (DWT) were presented, but the parallel input data sequence and the programmability of the 2-D DWT were rarely mentioned. In this paper, we present a parallel-processing VLSI architecture to compute the programmable 2-D DWT, including various wavelet filter lengths and various wavelet transform levels. The proposed architecture is very regular and easy to extend. To eliminate high frequency components, the pixel values outside the boundary of the image are mirror-extended as the symmetric wavelet transform and the mirror-extension is realized via the routing network. This design has been implemented and fabricated in a 0.35 /spl mu/m 1P4M CMOS technology and the working frequency is 50 MHz. The chip size is about 5200 /spl mu/m/spl times/2500 /spl mu/m. For a 256/spl times/256 image, the chip can perform 30 frames per second with the filter length varying from 2 to 20 and with various levels. Hence the proposed architecture is suitable for real-time applications such as JPEG 2000.
Type
journal article
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