Modelling, control and simulation of an IC wafer fabrication system: a generalized stochastic coloured timed Petri Net approach
Resource
International Journal of Production Research 38 (14): 3305-3341
Journal
International Journal of Production Research
Journal Volume
38
Journal Issue
14
Pages
3305-3341
Date Issued
2000
Date
2000
Author(s)
Lin, Ming-Hung
Abstract
This study presents a generalized stochastic coloured timed Petri net(GSCTPN) to model an IC wafer fabrication system. According to the GSCTPN, it models the dynamic behaviours of the IC fabrication system, such as loading, reentrant processing, unloading and machine failure. Furthermore, modular and synthesis techniques are used to construct a large and complex system model. The two major sub-models are the Process-Flow Model and the Transportation Model. The Transportation Model incorporates a simple motion-planning rule and a collision avoidance strategy to solve the variable speed and traffic jam problems of vehicles. This work also describes a simulation based performance analysis and schedule adjustment. To demonstrate the promise of the proposed work, this study makes actual Taiwanese IC wafer fabrication systems the target plant layout for implementation. © 2000 Taylor & Francis Group, LLC.
SDGs
Other Subjects
Computer simulation; Fabrication; Performance; Petri nets; Semiconductor device manufacture; Silicon wafers; Process-flow model; Integrated circuit manufacture
Type
journal article
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