Hardware Architecture of Tree Structure for Real-time Progressive Sequential Pattern Mining
Date Issued
2007
Date
2007
Author(s)
Chen, Bo-Han
DOI
en-US
Abstract
Traditional sequential pattern mining algorithms induce a significant amount of time. It is even worse on progressive database. In this paper, we design a hardware architecture to implement an efficient progressive sequential pattern mining algorithm. Our algorithm, HATS, uses a tree to maintain potential candidate sequential patterns in each sequence parallelly. With the pipeline design, HATS can generate candidate itemsets efficiently. We use software-hardware co-design technique on FPGA to design and verify our architecture. Our experimental result shows that HATS not only significantly outperforms competitive algorithms on synthetic datasets but also performs well on a real wireless gateway data. By processing wireless gateway log, the result of progressive sequential patterns mining provides a precise prefetching rule on wireless gateway, and minimizes the latency of mobile device query in a revolutionary way. Our design can also be adopted by other real-time applications of progressive sequential patterns mining.
Subjects
樹
資料探勘
累進式循序樣式探勘
硬體加速
結構設計
即時
可規劃邏輯閘陣列
Tree
Data Mining
Progressive Sequential Pattern Mining
Hardware-enhanced
Architecture Design
Real-time
FPGA
Type
thesis
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