A 28nm 20 TOPS/W in-Memory Search Engine with Pre-Charge-Free SRAM-Based TCAM and Hybrid-Match Mechanism for Few-Shot Learning
Journal
Proceedings - 2025 21st IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2025
Start Page
1
End Page
5
ISBN
[9798331589073]
Date Issued
2025-10-12
Author(s)
Abstract
This paper presents a 28nm in-memory search accelerator for few-shot learning (FSL), achieving 20 TOPS/W through co-optimization across circuit, architecture, and system levels. At the circuit level, a pre-charge-free SRAM-based TCAM macro is developed using inverter-driven matchline propagation and early mismatch bypassing to minimize latency and dynamic power. At the architecture level, we propose a Hybrid-Match post-processing mechanism that combines a relaxed Semi-Match condition with One-Hot detection to reduce search iterations and enhance prediction confidence. At the system level, we implement an optimized encoder that enables range-based similarity search with short codewords under the L∞ norm. Fabricated in 28nm CMOS, the chip reduces average search iterations from 14.57 to 1.75 and achieves 86.6% accuracy on a 32-way L-shot Om-niglot task, delivering a 25× improvement in energy efficiency compared to prior FSL accelerators. © 2025 IEEE.
Event(s)
2025 21st IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2025
Subjects
Content-addressable memory
Energy-efficient accelerator
Few-shot learning
In-memory search
Publisher
IEEE
Type
conference paper