A 6-b 800-MS/s Pipelined A/D Converter with Open-Loop Amplifiers

A 6-bit 800-MS/s pipelined A/D converter (ADC) achieves SNDR and SFDR of 33.7 dB and 47.5 dB, respectively. Employing voltage-mode open-loop amplifiers in gain stages, global gain control techniques, and two-bank-interleaved architecture, the proposed pipelined A/D converter relaxes stringent design tradeoffs between speed and power. Fabricated in a 0.18-μm CMOS technology, the ADC consumes 105 mW from a 1.8-V power supply while the active area is only 0.5 mm2. © 2007 IEEE.