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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
A simulation-based temporal assertion checker for PSL
Details
A simulation-based temporal assertion checker for PSL
Resource
Circuits and Systems, 2003. MWSCAS '03. Proceedings of the 46th IEEE International Midwest Symposium on
Journal
46th IEEE International Midwest Symposium on Circuits and Systems, 2003. MWSCAS '03
Pages
-
Date Issued
2003-12
Date
2003-12
Author(s)
Chang, Kai-Hui
Tu, Wei-Ting
Yeh, Yi-Jong
Kuo, Sy-Yen
DOI
10.1109/mwscas.2003.1562587
DOI
1548-3746
URI
http://ntur.lib.ntu.edu.tw//handle/246246/2007041910042753
http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910042753/1/01562587.pdf
Type
conference paper
File(s)
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Name
01562587.pdf
Size
656.04 KB
Format
Adobe PDF
Checksum
(MD5):6ce899a34fbdc7356ec0279c70f91fb9
