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College of Electrical Engineering and Computer Science / 電機資訊學院
Computer Science and Information Engineering / 資訊工程學系
On-chip bus architecture optimization for multi-core SoC systems
Details
On-chip bus architecture optimization for multi-core SoC systems
Journal
Lecture Notes in Computer Science
Journal Volume
4761 LNCS
Pages
301-310
Date Issued
2007
Author(s)
Lien, C.-M.
Chen, Y.-S.
CHI-SHENG SHIH
URI
http://www.scopus.com/inward/record.url?eid=2-s2.0-38149099199&partnerID=MN8TOARS
http://scholars.lib.ntu.edu.tw/handle/123456789/332146
Type
book
