Template-based Runtime Reconfiguration Scheduling For Partial Reconfigurable FPGA
Date Issued
2006
Date
2006
Author(s)
Chia, Li
DOI
en-US
Abstract
Reconfigurable hardwares can provide multiple functions with low cost and power consumption. Field Programmable Gate Array (FPGA), a form of reconfigurable hardware, is developing rapidly to handle high speed and complex applications. SRAM-based FPGA can be reconfigured during runtime to provide functionalities as they are required, thus reducing cost and power assumption. However, the reconfiguration delay time
and resource management of FPGA poses new challenges to traditional real-time scheduling algorithms. In order to optimize hardware usage and reconfiguration delay time, the scheduling and resource management on FPGA requires new techniques. In this thesis, we study the constraints of FPGA and propose a template-based approach to reuse hardware resources without compromising performances and violating the
reconfiguration deadline constraint. The proposed solution uses offline generated templates to assist the job of generating schedules during runtime.
Subjects
局部重組態
可程式化邏輯閘陣列
排程
可重組態硬體
partial reconfiguration
FPGA
scheduling
reconfigurable hardware
Type
thesis
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