Portable All-Digital Phase-Lock Loop Circuit Design With Programmable Pulse Width Control
Date Issued
2005
Date
2005
Author(s)
Wang, Wei
DOI
en-US
Abstract
The Phase-Locked Loop (PLL) is a widely used circuit for clock generator as system clock or Clock Data Recovery (CDR). A high-Speed architecture of Digitally-Controlled Oscillator (DCO) for All-Digital Phase-Locked Loop (ADPLL) is proposed for advanced specifications. The high-speed DCO is designed to operate from 140MHz to 1040MHz. The DCO core area is 345 um ´ 56 um. In addition, an area-efficient architecture is also introduced for low-cost applications. The hardware controller complexity can be reduced significantly. Prototype chips are both implemented with UMC 1P6M CMOS technology. The resolutions of both high-speed and area-efficient architectures are both achieved to 20ps.
The Pulse-Width-Controlled Loop (PWCL) is adopted to meet the demand for pulse-width-specific and high-speed CMOS application today. In the noisy SOC environment, analog components are easily influence by temperature, crosstalk and leakage capacitance voltage. We develop All-digital Pulse Width Control Loop (ADPWCL) architecture for future SOC applications. A prototype ADPWCL design is realized in UMC 0.18 1P6M process. With 5 pulse amplifier stage and 5 pulse shrinker stage, the functions of ADPWCL can be performed from 250 MHz to 1 GHz. The ADPWCL core area is 220 um ´ 180 um. Pulse width acquisition step is about 30ps.With the cooperation of ADPLL and ADPWCL, the on-chip clock has the characteristics of noise-insensitive, high-speed, and pulse-width-programmable.
Subjects
全數位式鎖相迴路
全數位式脈寬調整迴路
ADPLL
ADPWCL
Type
thesis
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