A Multiphase and a De-skew Clock Generator based on DLL
Date Issued
2010
Date
2010
Author(s)
Fong, Kevin
Abstract
DLLs are widely used in the multiphase clock generation. The conventional DLL only aligns the phase of the delayed output clock with the reference clock; therefore, the device mismatches induced by the process, voltage and temperature variation are not corrected by the loop and degrade the phase accuracy among each output clock. To mitigate the design constraint, a distributed DLL (DDLL) was proposed to achieve low jitter and high phase accuracy simultaneously.
However, the mismatches in PDs still degrade the phase accuracy among each output clock. To lessen the effect of the mismatch of the PDs, a PD rotation technique is proposed in this work along with the distributed DLL technique to further reduce the phase mismatch. The proposed DDLL is designed and fabricated in a 65-nm CMOS process. The experimental results indicate that the multiphase clock generator with self-calibration circuits is able to work with a power dissipation of 16 mW in a 1.45V power supply. The chip size is 0.95×0.95 mm2.
An all-digital de-skew clock generator for arbitrary wide range delay is proposed to minimize the instability of the clock settling while achieving fast locking time. The clock skew problem is detrimental in high-speed applications, especially when the skew is longer than multi-cycles. The proposed clock generator was fabricated in a 0.18-
Subjects
DLL
Type
thesis
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