A Robust and Design Flow Compatible Standard Cell Sizing Method for VLSI Circuit Performance Optimization
Date Issued
2014
Date
2014
Author(s)
Chen, Yi-Han
Abstract
In the VLSI circuit design flow, circuit optimization is a very important step especially for high performance and low power IC designs. The gate sizing technique has always been an effective method in delay, power dissipation and area trade-offs. Some existing methods use continuous approach to solve the gate sizing problem, which is based on the assumption that gate sizes can be any value within a certain range. Unfortunately, when using existing discrete standard cell libraries in real situation, the sizes available of a gate type are limited and sparsely distributed. Continuous methods thus suffers from rounding the continuous result back to discrete cell size, and often results in timing violations.
In this thesis, we provide a method to solve the discrete gate sizing problem by a dynamic programming solution searching method with a relaxation-restriction flow. The dynamic programming solution search can be applied to a directed acyclic graph with solution consistency relaxation. A speed-up solution merging technique is used in dynamic programming solution searching process. We determine the gate sizes following the dynamic programming solution while handling the inconsistency of reconvergence paths. Finally, a sensitivity guided heuristic algorithm is performed to reduce the area/power and further improves the circuit timing delay.
Experimental results show that our optimization results can beat the results generated by commercial tool when exhausted dynamic programming search is applied. With the speed-up solution merging technique applied, the optimization results can achieve comparable circuit delay while improving area and power dissipation.
Subjects
電路最佳化
元件尺寸最佳化
動態規劃
敏感度
減少面積
降低功率消耗
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-103-R00943142-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):d2459e1eca8434da46510806b1bce3b5