Low Ditof (2-4)× 1010using Y2O3epi-Si/Ge Gate Stacks
Journal
2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT)
Journal Volume
6
Start Page
189083
ISBN (of the container)
979-835033416-6
Date Issued
2023-04-17
Author(s)
Abstract
In this work, we have achieved record-low interfacial trap densities of (2-4) × 1010 eV-1cm-2 in the Y2O3/epi-Si/Ge(001) gate stacks, particularly low Dit less than 1 × 1011 eV-1cm-2 near the conduction band region. Synchrotron radiation photoemission was used to probe the interfacial bonding with atomic hydrogen exposure to elucidate the effect of post-metallization annealing in forming gas. After exposure of atomic hydrogen at 400°C, a great reduction of GeOx and a great increase of SiOx formation, which is stabilized in Si3+ states, suggest that the Y-O-Si formation attributed to the low Dit.
Publisher
IEEE
Type
conference paper