Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology
Journal
Proceedings - 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC 2014
Pages
109-112
Date Issued
2015
Author(s)
Abstract
Fully-integrated 40-Gb/s pulse pattern generator (PPG) and bit-error-rate tester (BERT) chipsets has been presented in 65-nm CMOS technology. Using external clock inputs, the PPG and BERT achieve full operation with ultra-wide data range from 40 Mb/s to 40 Gb/s. Built-in PLL and CDR circuits are also included to provide robustness for standard specification testing.
SDGs
Type
conference paper