Design of Received Signal Strength Indicator Circuit in CMOS Process
Date Issued
2016
Date
2016
Author(s)
Huang, Chao-Wei
Abstract
This thesis designs received signal strength indicator circuits (RSSI) by using successive detection logarithmic amplifier (SDLA) topology under TSMC 0.18μm and 40nm CMOS technology. Successive detection logarithmic amplifier composes of limiting amplifier, unbalanced source-coupled differential pair and low-pass filter. In design using 0.18μm CMOS process, the measurement results show that dynamic range of about 38dB from 0.1GHz to 1GHz, and dynamic range of 30dB from 1GHz to 2GHz. DC power consumption is 22.45mW, and chip size is 0.28 . In 40-nm CMOS process, the stimulation results show dynamic range with 40dB from 0.1GHz to 2.5GHz, and DC power consumption is 7.66mW with chip size of 0.06 mm2.
Subjects
received signal strength indicator circuit
successive detection logarithmic amplifier
limiting amplifier
unbalanced source-coupled differential pairs
Type
thesis