Design Methodology for Double Patterning Technology
Date Issued
2010
Date
2010
Author(s)
Hsu, Chin-Hsiung
Abstract
As IC technology continues to advance, lithography process meets the bottleneck due to printability and manufacturability. Double patterning technology (DPT) has recently gained much attention and is viewed as the most promising solution for the sub-32-nm node process, since it can increase the half-pitch resolution by up to two times using current infrastructures, thereby extending 193i wavelength beyond the 32-nm node and potentially down to the 16-nm node. DPT decomposes a layout into two masks and applies double exposure patterning to increase the pitch size and thus printability; conflict arises if layouts are not decomposable, and a stitch is induced if two touching sub-patterns of the same pattern are decomposed into different masks. However, the existing design flow is not compatible with DPT since resulting layouts with patterns are not decomposable. Therefore, it is desirable to develop a DPT-compliant design flow that focuses on strongly DPT-related stages, including (1) layout-migration-based cell design, (2) global routing, and (3) detailed routing. Besides, the cost of doubling masks is also an important problem for DPT, so our DPT-compliant design flow would minimize the number of masks for DPT.
Layout-migration-based cell design becomes very popular as IC technology continues to advance very quickly and manual cell design is very time-consuming. Layout migration and DPT layout decomposition become two closely related problems for DPT-aware cell design. Therefore, we present the first algorithm in the literature for the simultaneous layout migration and decomposition (SMD) problem. Our algorithm first constructs a potential conflict graph and DPT-aware constraint graphs, and then applies integer linear programming (ILP) corresponding to the graphs to obtain a decomposed and migrated layout. We further present an effective graph-based reduction technique to prune the ILP solution space. In addition, we present an approach to generate DPT-aware standard cells by considering the DPT effects on the cell boundaries to handle the DPT issues in the weakly-pattern-related placement stage.
Routing is a very complex process in a modern chip, so routing is often divided into global routing and detailed routing; global routing generates a loose route for each net while detailed routing finds the actual geometric layout of nets. Global routing is an important step for physical design, but existing global routing congestion models ignore DPT effects and reasonable via usage for routing through multiple metal layers. Such simplified models would easily cause fatal routability and DPT-compliant problems in the subsequent detailed routing. To remedy this deficiency, a more effective congestion metric that considers both the DPT effects and the reasonable via usage for global routing is presented. With this metric, we develop a new multi-layer global router that features two novel routing algorithms, namely aerial-monotonic routing and escaping-point routing.
Detailed routing is an important step to make layouts DPT-compliant since it decides actual geometric layout of nets; besides, it also has an opportunity to reduce the number of masks for DPT. We proposes the first mask-sharing methodology for DPT, which can share masks among different designs, to reduce the number of costly masks for double patterning. The design methodology consists of two tasks: template-mask design and template-mask-aware detailed routing. A graph matching-based algorithm is developed to design a flexible template mask that tries to accommodate as many design patterns as possible. We also present a template-mask- aware detailed routing (TMR) algorithm, focusing on DPT-related issues to generate routing solutions that satisfy the constraints induced from double pattern ing and template masks.
Experimental results show that, compared with the non-DPT-compliant design flow, our DPT-compliant design flow can achieve smaller layout area, fewer stitches, and shorter wirelength with reasonable via and runtime overheads. In addition, our DPT-compliant design flow can obtain conflict-free layouts and totally save eight masks for DPT while the non-DPT-compliant design flow cannot. The results show the effectiveness of our DPT-compliant design flow and the compatibility between our DPT-related techniques and existing electronic design automation (EDA) tools.
Subjects
Double Patterning
Manufacturability
Physical Design
Routing
VLSI
SDGs
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-99-F94943075-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):7d707a16ff0f9ac0c571bc97ecd55fca