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  4. The Design and Implementation of Spread Spectrum Clock Generators Using a Novel Capacitance Multiplication Method
 
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The Design and Implementation of Spread Spectrum Clock Generators Using a Novel Capacitance Multiplication Method

Date Issued
2009
Date
2009
Author(s)
Kuo, Chung-Yui
URI
http://ntur.lib.ntu.edu.tw//handle/246246/189164
Abstract
Electronic components often generate radiated electromagnetic interference (EMI)that affects the operations of nearby components. It becomes a serious problem that faster operating speeds result in more EMI. It has been proved that the spread spectrum clocking can reduce the peak power into a controllable range, thus achieving EMI reduction effectively. A spread spectrum clock generator (SSCG) is a phase locked loop (PLL) with appropriate frequency-modulated output. One of themplemental methods involves direct modulation of the voltage controlled oscillator (VCO) in PLL. But theoop bandwidth should be much smaller than the modulation frequency to allow frequency variation; i.e. there should be large passive components, especially capacitors as using this method. Similarly, the small bandwidth is also required for stability when a small input reference is applied to a PLL. In this thesis, a modified dual-path loop filter is presented. This configuration can have a multiplication ratio more than n. This configuration is applied to the SSCG as well. Chapter 1 gives a brief summary of the PLL, including its applications, linear model, related noise source, and issues among each block. Chapter 2 focuses on the basic properties of SSCG, different profiles on the spectrum, timing impacts within spread spectrum, and summarizes the circuit implementation methods of the SSCG. Chapter 3 provides a technique for capacitance multiplication utilized in the low pass filter (LPF). We will give a detailed description and compare the proposed one with the previous work using Simulink simulator. In chapter 4, an SSCG with direct modulation on VCO and based on the technique mentioned in chapter 3 is presented, fabricated in 0.18-μm TSMC CMOS process. Thexperimental results of this chip are also presented. The experimental results also confirm that different modulation profiles result in different EMI reduction. Chapter 5 implements another SSCG used for X-band application. A simple feedback compensation mechanism added in the original charge pump is presented. Theections contain the circuit descriptions of each building block and list some cautions when layout and designing. We also leave some conclusions and recommendations for future work at the end of this thesis.
Subjects
Electromagnetic interference (EMI)
Spread spectrum clock generator (SSCG), Phase locked loop (PLL)
Voltage controlled oscillator (VCO)
Low pass filter (LPF)
Type
thesis
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ntu-98-R95943006-1.pdf

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(MD5):6f5e7fb16750f3f7e69db7b0bf7921c5

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