Deadlock Checking of SystemC Designs Using Extended Petri-Net Model
Date Issued
2009
Date
2009
Author(s)
Cai, Siao-Jie
Abstract
As SystemC is becoming the prevailing modeling language to handle the increasing complexity of the modern system-level designs, tools to conduct fast and accurate simulation and perform solid functional verification on SystemC designs have become the most critical component in the design flow. Since conventional compiled code simulators compile the SystemC designs into low-level executable programs, they can only perform simulation-based validation. Therefore, it is virtually impossible to further analyze the design functionality for the non-trivial design errors such as dead-lock condition. n this thesis, we proposed an extended Petri-Net model for SystemC designs. We also implemented a SystemC simulator based on this model. With the internal representation of the SystemC designs and the controllability on the simulation scheduling, we are able to perform the deadlock checks of the SystemC designs. Our proposed algorithm first analyzes the dependencies of the event synchronization for the concurrent processes in the SystemC design. And a graph data structure is then presented to help designers to figure out the causes of the deadlock. We will demonstrate the correctness of the proposed model and the deadlock checking through several working examples. urthermore, the proposed extended Petri-Net model can also act as a formal representation of a SystemC design. This brings up a lot of possibilities for the research with formal verification techniques in the future.
Subjects
deadlock
simulation validation
electronic system level
Type
thesis
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