A 4-PAM Adaptive Analog Equalizer for Backplane Interconnections
Date Issued
2006
Date
2006
Author(s)
Chen, Qui-Ting
DOI
en-US
Abstract
The exploring increasing of data rate has created a major challenge for electronic circuits used at the interface of the backplane physical layer links. As the data rate increases above Gb/s, intersymbol interference (ISI) becomes an essential issue in digital communications, limiting the achievable transmission speed and distance over channels.
As to electronic compensation for the channel loss, digital or analog equalizers can be used. Digital (DSP based) equalization offers more accurate and higher performance comparing with analog counterpart. But the design of digital equalization has a bottleneck on the implementation of high-speed ADCs, which need large area and high power consumption. Consequently, pure analog equalizer is a more efficient solution.
In this thesis, a 4-PAM (pulse amplitude modulation) adaptive analog equalizer is proposed to compensate the FR-4 PCB backplane interconnections by using a sum-feedback filter (SFF), relaxing the design requirement of the conventional analog feed-forward equalizers (FFE). 4-PAM is also adopted to increase the transmission data rate over bandwidth-limited channel. Fabricated in a standard 0.18-μm CMOS technology, the analog equalizer can successfully recover the 14 Gb/s random data transmitted over 40-inch copper channels while dissipating 121 mW from a 1.8-V power supply. The die size is 1.285 × 0.98 mm2.
Subjects
振幅調變
等化器
PAM
equalizer PCB
Type
thesis
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