A 4th-Order CTDSM with PVT-Insensitive Inverter-Based OTAs
Journal
2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)
Part Of
2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings
ISBN (of the container)
979-835036034-9
Date Issued
2024-04-22
Author(s)
Ming-Wei Kung
Abstract
This paper presents a 4th-order CTDSM with PVT-insensitive inverter-based OTAs. In order to make CTDSM adapted for technology migration, the inverter-based OTA is used in the loop filter, which is easier to scale with better linearity. An LDO that can automatically adjust the supply voltage is proposed to solve the PVT variation. With the replica inverter unit, the trip point of the inverter can be tracked. Therefore, the inverter-based OTA can have stable small-signal performance; eventually, the CTDSM has more than 70 dB over PVT. The prototype CTDSM has been fabricated in 28-nm CMOS technology. It achieves 72.22-dB SNR and 71.92-dB SNDR over the bandwidth of 1 MHz and consumes 0.4mW at a 0.7V supply.
Event(s)
2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA
SDGs
Publisher
IEEE
Type
conference paper