Architecture Design of Configurable Thread Culling Unit for Mobile GPUs
Date Issued
2011
Date
2011
Author(s)
Yu, Meng-Lin
Abstract
GPU becomes popular in modern computing devices due to its outstanding processing ability. Modern GPUs usually consist of multiprocessors that are suitable for parallel processing. As the design of GPU becomes more general in recent years, not only traditional 3D graphics rendering but also many general applications tend to utilize the plentiful resources on GPU.
For mobile GPUs, the computing resources are rather limited; therefore some techniques should be established to reduce workload. It is known that the rendering operations of occluded objects should be avoided in 3D graphics applications. Moreover, for some applications which exploit region of interest (ROI) processing, only the operations in the ROI should be executed. In order to reduce the computation with the above-mentioned concepts, in this thesis, a con gurable thread culling unit (TCU) is proposed to enhance the performance of mobile GPUs.
TCU can be con gured into two operating modes and performs at both tile and pixel levels. First, for 3D rendering applications, an early Z test is employed to remove occluded regions and detect visible regions. Experimental results show that in average 14-% of pixels are discarded, 15-% of pixels
are marked as visible and the speed up of 1.1 can be achieved compared to the case where no culling is carried out. Second, an early stencil-like test is executed to discard non-interested regions in ROI processing. Experimental results show that compared to predicate execution, the performance is enhanced by 25 and 6 for Viola-Jones face detection and Gabor feature extraction in salient region, respectively.
Finally, the proposed design is integrated into GPU and is veri ed in hardware implementation. Designed with TSMC 65-nm technology, less than 5% total area is increased with TCU, including a 1KB cache, which shows that the hardware cost overhead of proposed TCU is quite small. Furthermore, the GPU system is prototyped on a FPGA platform and the function has been veri ed, where about 40K slices are utilized in Xilinx Vertex-5 XC5VLX330.
Subjects
GPU
thread culling
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-100-R98943011-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):042a87589f3e90684162bb398754352f