Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits
Journal
Journal of Electronic Testing: Theory and Applications (JETTA)
Journal Volume
37
Journal Issue
4
Pages
453-471
Date Issued
2021
Author(s)
Abstract
It is a real challenge to test asynchronous circuits since there is no clock signal, and there are many non-scan state-holding elements. In this paper, we first propose an Asynchronous Circuit Scan (A-SCAN) latch, which can flip between Valid and Empty states so that we can shift in and out without any clock. Experimental results show that our DFT area and power overhead are 28% and 104% smaller than previous synchronous DFT, respectively. The timing overhead of DFT is nearly two times smaller than previous asynchronous DFT. Based on A-SCAN, we propose the Asynchronous Built-in Self Test (A-BIST), which has no clock. Experimental results show that our BIST area and power overhead are 30% and 116% smaller than previous synchronous counterpart, respectively. Our test coverage is similar to that of ATPG. With A-SCAN and A-BIST, we can easily integrate synchronous and asynchronous testing on the same chip. ? 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.
Subjects
Asynchronous circuits
Build-in self test
Design for testability
Dual-rail
Low power test
Asynchronous sequential logic
Built-in self test
Clocks
Integrated circuit testing
Low power electronics
Area overhead
Build in self tests
Builtin self tests (BIST)
Clock signal
Design-for-testability
Dual rail
EmptyState
Low-power tests
Power overhead
Timing circuits
SDGs
Type
journal article