Exploiting Bank-level Parallelism via Data Consistency Relaxation for Non-volatile Memory System
Date Issued
2015
Date
2015
Author(s)
Wang, Shao-Fu
Abstract
The maturity of emerging non-volatile memory (NVM) technologies presents promising next-generation memory system design. Because of its mixed performance characteristics between DRAM and persistent store, e.g., high density, byte-addressability, and non-volatility, architects rethink the design of traditional memory hierarchy. With NVM as main memory, programmer can place non-volatile data structures on main memory and directly access them by ld/st instructions. Non-volatile data structures demand consistency and atomicity guarantees in case of sudden system crash. To guarantee consistency and atomicity, some forms of write-ahead logging (WAL) semantics are needed. Because modern memory controller reorders writes to exploit bank-level parallelism, persist barrier is adopted by many existing works to guarantee the order between writes. However, we observe that persist barriers introduce unnecessary write ordering constraints and hurt the system performance by restricting memory controller from exploiting bank-level parallelism. In this thesis, we propose Semantics-aware Memory Scheduler. By using a new software/hardware interface to transfer knowledge of application''s logging semantics to memory controller, Semantics-aware Memory Scheduler eliminates unnecessary write ordering constraints by differentiating between log writes and target data writes. Through allowing more concurrent memory writes, memory controller can provide more performance by maximizing bank-level parallelism. Experimental results of full-system simulation show that Semantics-aware Memory Scheduler can improve throughput by up to 2.89x (2.13x on average).
Subjects
Non-volatile Memory
Storage Class Memory
Phase-change Memory
Memory Scheduler
Memory Management
Consistency
Type
thesis
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ntu-104-R02922070-1.pdf
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