Memory System Characterization of Multimedia Application on Multi-Core Platform
Date Issued
2009
Date
2009
Author(s)
Lin, Tzu-Ching
Abstract
The memory system has been a major bottleneck in system design. Due to the rapidly increasing gap between memory and processor performance, the bottleneck becomes even more critical for memory-intensive applications that process large volumes of data under demanding throughput, cost and power constraints. In this thesis, we target at H.264 executing on a dual-core architecture. The goal of this thesis is to characterize the memory system behavior, identify the system performance bottlenecks, and give insights for performance improvement. The dual-core system is composed by an ARM processor and a PACDSP core, which is a DSP developed by ITRI. The first step of this project is to establish the simulation environment. With the simulation environment, we can study system performance with various system configurations. In this thesis, we will show how we built the simulation environment, and the system performance characterization results with both single-bus and multi-bus architecture. Moreover, we will also identify the reasons to cause performance bottlenecks, and propose solutions to improve system performance.
Subjects
memory system
workload characterization
hw/sw co-simulation framework
Type
thesis
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