Fault-tolerant On-chip Network Architecture for 2D-mesh Based Chip Multiprocessor Systems
Date Issued
2009
Date
2009
Author(s)
Hsu, Chan-cheng
Abstract
In this thesis, to improve fault-tolerance and reduce performance degradation in faulty on-chip networks, two on-chip network (OCN) architectures are proposed: 1) 20-path router (20PR), a router embedded with Built-in Self-Test/Self-Diagnosis (BIST/BISD) and Fault-Isolation (FI) circuits. 2) Surrounding Test Ring (STR), an external test architecture which externally perform test and diagnosis of the on-chip network. They embed BIST/SD and FI circuits that detect, locate, and isolate the impacts of the faulty FIFOs and MUXs in the faulty routers. Moreover, 20PR and STR apply undamaged datapaths in faulty routers to reduce performance degradation. The operation system can remap the tasks onto undamaged datapaths the proposed architectures found to maintain system function.n our experiments, the BIST/SD of the 20PR can be executed in 117 constant test cycles and the STR can be executed in 144~376 test cycles. The overhead of the OCN using 20PRs increases 15.17%, while the OCNs with STRs increase 8.48%~13.3%. The experiments also show the performance improved over prior approaches which completely disable faulty routers. The remapped packets are reduced by 75.68%~83.29% for 20PR and 68.33%~79.31% for STR comparing to traditional approaches. The system latencies are also reduced by 7.25%~24.57% for 20PR and 4.86%~23.6% for STR comparing to traditional approaches. The experiment shows proposed fault-tolerant OCN architectures can perform graceful degradation in faulty mesh OCNs.
Subjects
On-chip Network
Fault-tolerant Design
Built-in Self-test
Built-in Self-diagnosis
Type
thesis
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