A 1600-MIPS parallel processor IC for job-shop scheduling
Journal
IEEE Transactions on Industrial Electronics
Journal Volume
52
Journal Issue
1
Pages
291-299
Date Issued
2005
Date
2005
Author(s)
Abstract
A job shop is a typical environment for manufacturing low-volume and high- variety discrete parts, where parts are of various due dates, priorities, and sequences of production operations. Good scheduling of when to do what using which resource is critical and challenging for the competitiveness of job shops. The Lagrangian relaxation neural network (LRNN) presented by Luh et al. provides an effective solution to this problem. To further speed up the scheduling of large problems, the parallelism of the LRNN approach is exploited in this paper for hardware implementation. A parallel processor based on the single-instruction multiple-data-stream architecture and its associated instruction set are designed. The architecture is implemented in a single-poly quadruple-metal 0.35-μm CMOS technology. Test results shows that the fabricated chip achieves 10 and 30 times speed-up when compared with several commercial digital signal processor chips and a 600-MHz PC, respectively. © 2005 IEEE.
Subjects
Job-shop scheduling; Lagrangian relaxation neural network (LRNN); Single-instruction multiple-data-stream (SIMD)
SDGs
Other Subjects
Algorithms; CMOS integrated circuits; Dynamic programming; Lagrange multipliers; Neural networks; VLSI circuits; Job shop scheduling; Lagrangian relaxation neural network (LRNN); Neuron based dynamic programming; Single instruction multiple data stream (SIMD); Integrated circuit manufacture
Type
journal article
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