Test Compression for Neuromorphic Chips
Journal
2024 IEEE European Test Symposium (ETS)
Part Of
Proceedings of the European Test Workshop2024
ISBN (of the container)
979-835034932-0
Date Issued
2024-05-20
Author(s)
Abstract
We propose test compression techniques to reduce the test time (test configurations and test length) for neuromorphic chips. Our test compression techniques include Dynamic Test Compression (DTC) and Static Test Compression (STC). DTC generates test configurations with machine learning. STC reduces test length under the constraint of the significance level in Two-sample Hotelling’s T-square Test. Experiments on two neuromorphic architectures show that our proposed techniques can reduce the total test configurations by 90.44% and the total test length by 93.47%, respectively. Our run time is more than 10x faster than the previous method. The proposed techniques are independent of neuromorphic chips’ applications.
Event(s)
29th IEEE European Test Symposium, ETS 2024
Publisher
IEEE
Type
conference paper